Tri-gate device with conformal pvd workfunction metal on its three-dimensional body and fabrication method thereof

ABSTRACT

A method of fabricating a tri-gate semiconductor device comprising a semiconductor body having an upper surface and side surfaces and a metal gate that has an approximately equal thickness on the upper and side surfaces. Embodiments of a tri-gate device with conformal physical vapor deposition workfunction metal on its three-dimensional body are described herein. Other embodiments may be described and claimed.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional application of Ser. No. 11/418,295filed May 3, 2006, entitled “TRI-GATE DEVICE WITH CONFORMAL PVDWORKFUNCTION METAL ON ITS THREE-DIMENSIONAL BODY AND FABRICATION METHODTHEREOF”.

FIELD OF THE INVENTION

The field of invention relates generally to the field of semiconductorintegrated circuit manufacturing and more specifically, but notexclusively, relates to complementary metal oxide semiconductor (CMOS)devices having a conformal metal gate structure on a three-dimensionaltri-gate fin body.

BACKGROUND INFORMATION

In a conventional metal oxide semiconductor field effect transistor(MOSFET), the source, channel, and drain structures are constructedadjacent to each other within the same plane. The gate dielectric isformed on the channel area and the gate electrode is deposited on thegate dielectric. The transistor is controlled by applying a voltage tothe gate electrode thereby allowing a current to flow through thechannel between source and drain. The area necessary to support thesestructures in a plane constrains the number of transistors that can beplaced within the limited area of a semiconductor chip. Semiconductormanufacturers increase the packing density of transistors by scalingdown the size of the transistor at each generation of technology.

With advances in technology, the physical dimensions of the gatedielectric thickness, the gate length, and the gate oxide thickness havebeen reduced significantly. Contemporary manufacturing methods currentlyallow semiconductors to be produced with a transistor gate length of 45nanometers (nm) and a gate oxide thickness of about 1.2 nm. Oneconventional gate oxide, silicon dioxide, exhibits reliability issueswhen only a few atomic layers thick. Additionally, this very thin gateoxide allows leakage current to pass when the device is in an off state,thereby leading to high levels of power consumption and excess heatgeneration in the semiconductor chip.

Alternative gate dielectric materials have been introduced to helpalleviate this problem. However, due to material incompatibilityproblems, the alternative gate dielectric materials have necessitated achange in gate electrode materials. The polysilicon that has been usedas a gate electrode material for many generations is now being replacedwith a metal gate. Fabrication of the device using a metal gate insteadof a polysilicon gate allows the threshold voltage of a transistor to bebetter controlled.

An alternative to the standard methods of building planar MOSFETs hasbeen proposed to help alleviate some of the physical barriers to scalingdown existing designs. These proposals involve the construction of threedimensional MOSFETs either in the form of a dual-gate transistor(FinFET) or as a tri-gate transistor as a replacement for theconventional planar MOSFET.

Three-dimensional transistor designs such as the dual-gate FinFET andthe tri-gate transistor allow tighter packing of the same number oftransistors on a semiconductor chip by using vertical or angled surfacesfor the gates. The designers use vertical space to accommodate the extratransistor gates, which is analogous to building multi-level buildingsas opposed to building single story buildings over a larger plot ofland. In a dual-gate FinFET, two gates are oriented along a very narrowstrip of silicon known as a fin. The two gates have equivalent lengthsbecause they are located along opposite sides of the fine. The physicalsize of the fin is typically on the order of 10 nm in width and 50 nm inheight. A tri-gate device consists of three gates on a semiconductorbody whereby the physical dimensions of the sides of the semiconductorbody are equal, resulting in three equivalent transistor gate widths onthe same semiconductor body.

Since the tri-gate device has one top gate and two side gates, theoverall threshold voltage (V_(t)) of the tri-gate device is a functionof the V_(t) contributed by the top gate and the V_(t) for each of thetwo side gates. The V_(t) of a transistor is a critical parameter in theoperation of the transistor. When a voltage is applied to a gate, theelectrons in the substrate become concentrated in the region of thesubstrate nearest the gate creating a depletion region, or a regionwhere the concentration of electrons are equal to the electron holes. Ifthe voltage applied to the gate is below the threshold voltage, thetransistor will remain in an off state. If the voltage applied to thegate is above the threshold voltage, then the transistor is turned onand current is allowed to flow from the source to the drain.

The V_(t) is a function of the materials used for the conductor, such asa polysilicon layer and a metal layer, along with the respectivethicknesses of these layers. One problem with the current method offabricating a tri-gate device is that the V_(t) for the top gate may bedifferent than the V_(t) contributed by each of the two side gates. As aresult, when a tri-gate device with equal width gates on the top and twosides of the device is scaled, the V_(t) for the top gate scalesdifferently than the V_(t) contributed by the two side gates. It wouldbe an advance in the art to construct a tri-gate device whose physicaldimensions can be scaled while maintaining an equivalent V_(t) on allthree gates.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing aspects and many of the attendant advantages of thisinvention will become more readily appreciated as the same becomesbetter understood by reference to the following detailed description,when taken in conjunction with the accompanying drawings, wherein likereference numerals refer to like parts throughout the various viewsunless otherwise specified:

FIG. 1 is a flowchart describing an example fabrication process used tocreate a workfunction metal with a nearly equivalent metal gatethickness on three surfaces of a tri-gate semiconductor device.

FIG. 2 is an illustration of a cross-sectional view of two tri-gatedevices after forming a physical vapor deposition (PVD) workfunctionmetal.

FIG. 3 is an illustration of the structure of FIG. 2 with a sacrificialmasking layer deposited as a blanket layer.

FIG. 4 is an illustration of the structure of FIG. 3 with a top portionof the sacrificial masking layer removed to expose a top surface of theworkfunction metal on a top gate.

FIG. 5 is an illustration of the structure of FIG. 4 with a thinnedworkfunction metal on the top gate.

FIG. 6 is an illustration of the structure of FIG. 5 with the remainingsacrificial masking layer removed.

FIG. 7 is an illustration of the structure of FIG. 6 with a polysiliconlayer deposited on the thinned workfunction metal.

DETAILED DESCRIPTION

Embodiments of methods and apparatus for a tri-gate device with aconformal workfunction metal of nearly equivalent thickness on all threegates are described herein. In the following description, numerousspecific details are set forth in order to provide a thoroughunderstanding of embodiments of the present invention. One skilled inthe relevant art will recognize, however, that the invention can bepracticed without one or more of the specific details, or with othermethods, components, materials, etc. In other instances, well-knownstructures, materials, or operations are not shown or described indetail to avoid obscuring aspects of the invention.

Reference throughout this specification to “one embodiment” or “anembodiment” means that a particular feature, structure, orcharacteristic described in connection with the embodiment is includedin at least one embodiment of the present invention. Thus, theappearances of the phrases “in one embodiment” or “in an embodiment” invarious places throughout this specification are not necessarily allreferring to the same embodiment. Furthermore, the particular features,structures, or characteristics may be combined in any suitable manner inone or more embodiments.

An example for how a conformal metal with a pre-determined work functionhaving a nearly equivalent thickness on all three sides of a tri-gatetransistor can be formed is described in FIG. 1. A workfunction metal isa metal with a known work function, which is an inherent characteristicof the metal. FIG. 1 describes an embodiment whereby a workfunctionmetal is formed on three surfaces of a semiconductor body and theworkfunction metal on a top surface of the semiconductor body is erodedto create a metal gate on all three surfaces that has a consistentthickness. The process is initiated (element 100) by forming theworkfunction metal on the top and two side surfaces of a semiconductorbody. The semiconductor body may be formed, for example, from amonocrystalline substrate or from a silicon-on-insulator (SOI) layer.The three surfaces of the semiconductor body may be coated with a thindielectric layer which may comprise a silicon oxide, or alternatively, ahigh-k dielectric layer such as lanthanum oxide, tantalum oxide,titanium oxide, hafnium oxide, zirconium oxide, lead-zirconate-titanate(PZT), barium-strontium-titanate (BST), or aluminum oxide. In oneembodiment, the high-k dielectric layer is between 15 angstroms and 30angstroms in thickness, although these values for the dielectric layerare not limiting.

The workfunction metal can be formed using a directional sensitive PVDmetal deposition process whereby ions of an inert gas are acceleratedtowards a workfunction metal target, which may comprise titanium nitride(TiN), tantalum nitride (TaN), or another transition nitride metal. Uponimpact, the ions from the inert gas sputter-off a target material andthe target material forms on the surface of the tri-gate device in ananisotropic manner. The deposition rate depends on the angle ofincidence of incoming particles, resulting in a higher deposition rateon the top gate than the side gates of the tri-gate device. Depositionof the workfunction metal layer using the PVD process is characterizedby a microstructure that comprises columnar grains.

In another embodiment, a workfunction metal layer may be formed usinganisotropic layering techniques including molecular beam epitaxy (MBE),chemical vapor deposition (CVD), electroplating, or evaporation. In oneembodiment, a target thickness of the workfunction metal layer isbetween 25 angstroms and 300 angstroms in thickness. The workfunctionmetal layer thickness selected by the device designer is a function ofthe targeted V_(t) for the tri-gate device.

After forming the workfunction metal layer, a sacrificial masking layer(element 102) is deposited as a blanket layer. The sacrificial maskinglayer is applied to mask and planarize vertical features on the wafer.In one embodiment, the sacrificial masking layer may be a thick layer(1100-1500 angstroms) of a sacrificial light absorbing material (SLAM).SLAM is a material that covers the surface of the wafer by filling viasand normalizing a topography, thereby providing a consistent hole-freeand opaque surface. The sacrificial masking layer may comprise anotherorganosiloxane film such as bottom anti-reflective coating (BARC) or anorganic spin-on coating such as photoresist.

The sacrificial masking material is etched (element 104) to remove a topportion of the material to expose the workfunction metal on the top gateof the tri-gate device. The sacrificial masking material may bedry-etched using sulfur hexafluoride (SF6), octafluorocyclobutane(C4F8), or another fluorocarbon (CxFy) gas in a plasma enhanced chemicalvapor deposition (PECVD) chamber. The dry-etch process may be terminatedby sensing a workfunction metal surface on the top gate of the tri-gatedevice. However, the sacrificial masking material may also be erodedusing a wet-etch process. In one embodiment, the wet-etch process maycomprise HF or hydroxide containing solutions.

The workfunction metal on the top gate of the tri-gate device is eroded(element 106) so that the thickness of the workfunction metal on the topgate is nearly equal to the thickness of the workfunction metal on thetwo side gates of the tri-gate device. In one embodiment, theworkfunction metal on the top gate of the tri-gate device is erodedusing sulfur hexafluoride (SF6), octafluorocyclobutane (C4F8), oranother fluorocarbon (CxFy) gas in a PECVD chamber. The two side gatesare protected from erosion by the sacrificial masking material duringthis process and maintain their initial thickness. As a result, thethickness of the workfunction metal on the two side gates of thetri-gate device are left unchanged. Other erosion techniques may beemployed to achieve equivalent results. Examples may include wet-etch,chemical mechanical polishing (CMP) or ion milling techniques.

The remaining sacrificial masking material may be stripped or removed(element 108) once a desired workfunction metal thickness has beenachieved on the top gate of the tri-gate device. In one embodiment, theremaining SLAM material is removed using an aqueous buffered hydrogenfluoride (HF) stripping solution. The stripping solution shouldselectively remove the sacrificial masking material without eroding amaterial amount of the workfunction metal.

After removing the remaining sacrificial masking material, theworkfunction metal is clean and free of polymer residue and a topsurface of the workfunction metal is suitable for further processing. Inone embodiment, a polysilicon layer may be deposited on the top surfaceof the workfunction metal. A polysilicon layer may be deposited tocreate a vertical or nearly vertical wall adjacent to a side gate of atri-gate device. A polysilicon layer may also be deposited to protectthe workfunction metal (element 110) from interacting with an atmosphereor during subsequent processing steps that would be harmful to aworkfunction metal surface.

In one embodiment, a workfunction metal formed as a top gate of atri-gate transistor is noticeably thicker than the workfunction metalformed as two side gates, as illustrated in FIG. 2. A semiconductor body200 constructed from a silicon substrate is formed to create gateregions that are separated by a silicon dioxide layer 210. A gatedielectric layer 220 covers the silicon dioxide layers 210 and the gateregions. A workfunction metal 230 is then formed on the gate dielectriclayer 220. The workfunction metal 230 may be a metal film such astungsten, tantalum, titanium and/or nitrides and alloys thereof. For nchannel-type transistors, the workfunction metal 230 provides a workfunction in the range of 3.9 to 4.6. For the p channel-type transistors,the workfunction metal 230 provides a work function of 4.6 to 5.2 eV.Accordingly, for substrates with both n channel and p channeltransistors, two separate metal deposition processes may need to beused.

The workfunction metal 230, such as TiN is formed as a layer on thesurface of the dielectric layer 220 on all three gates of the tri-gatedevice. The TiN layer may be formed by using physical vapor deposition(PVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE),chemical vapor deposition (CVD), electroplating, or evaporation.

After forming the workfunction metal layer 230, a sacrificial maskinglayer 300 is deposited as a blanket layer as illustrated in FIG. 3. Thesacrificial masking layer 300 is applied to mask and planarize thevertical features. In one embodiment, the sacrificial masking layer 300may be a SLAM layer with a thickness of 1100 angstroms to 1500angstroms. The sacrificial masking layer 300 may also be aorganosiloxane layer such as bottom anti-reflective coating (BARC) or anorganic spin-on coating such as photoresist.

A top portion 400 of the sacrificial masking layer 300 is removed toreveal the workfunction metal 230 on the top gate of the tri-gatedevice, as shown in FIG. 4. The sacrificial masking layer 300 is eroded,resulting in a surface 400 that is below a top surface of theworkfunction metal 230 on a top gate of the tri-gate device. In oneembodiment, the sacrificial masking layer 300 may be dry-etched usingsulfur hexafluoride (SF6) in a PECVD chamber.

After etching a top portion of the sacrificial masking layer 300, theworkfunction metal 230 on the top gate of the tri-gate device is eroded,as illustrated in FIG. 5, so that the thickness of the workfunctionmetal 230 on the top gate is nearly equivalent to the thickness of theworkfunction metal 230 on two side gates of the tri-gate device. Anupper surface of the sacrificial masking layer 500 may be minimallyeroded depending on the process used to etch the workfunction metal 230on the top gate. For instance, if a dry-etch process is used to erodethe workfunction metal 230 on the top gate, the etch process may alsoconsume a small amount of an upper portion of the sacrificial maskinglayer 500. The amount removed is dependent on the selectivity of theetch chemistry. Once eroded, a thickness of the workfunction metal 230on the top gate 510 of the tri-gate device will be nearly equivalent tothe thickness of the two side gates. In one embodiment, the thickness ofthe workfunction metal 230 on the top gate of the tri-gate device willmatch the thickness of the workfunction metal 230 on the two side gatesof the tri-gate device within a maximum deviation of +/−10%.

FIG. 6 illustrates an embodiment after the sacrificial masking layer 300has been stripped from the workfunction metal 600. In one example, thethickness of the workfunction metal 600 on the top gate of the tri-gatedevice may be nearly equivalent to the thickness of side gates 610 and620.

FIG. 7 illustrates another embodiment where a polysilicon layer 700 isdeposited on a workfunction metal of a tri-gate device with aworkfunction metal layer that has a nearly equivalent thickness on a topsurface and two side surfaces of a semiconductor body. The polysiliconlayer 700 is normally doped for reduced resistance and is used to createa conductive path to the workfunction metal 600. The polysilicon layer700 may be deposited to create a vertical or nearly vertical walladjacent to a side gate of a tri-gate device. The thickness of thepolysilicon layer 700 may range for example from a minimum of 400angstroms and a maximum of 1200 angstroms. The polysilicon layer 700 maybe doped or un-doped and can be used to protect the workfunction metal600 from interaction with an atmosphere or during subsequent processingsteps that would be harmful to the workfunction metal surface. Forexample, a subsequent processing step may contain aqueous acids, bases,or oxidizers that would erode or modify the surface of the workfunctionmetal.

The above description of illustrated embodiments of the invention,including what is described in the Abstract, is not intended to beexhaustive or to limit the invention to the precise forms disclosed.While specific embodiments of, and examples for, the invention aredescribed herein for illustrative purposes, various equivalentmodifications are possible within the scope of the invention, as thoseskilled in the relevant art will recognize.

These modifications can be made to the invention in light of the abovedetailed description. The terms used in the following claims should notbe construed to limit the invention to the specific embodimentsdisclosed in the specification and the drawings. Rather, the scope ofthe invention is to be determined entirely by the following claims,which are to be construed in accordance with established doctrines ofclaim interpretation.

1. A semiconductor apparatus comprising: a semiconductor body having atop surface and laterally opposite sidewalls; a metal gate withapproximately equal thickness on the top surface and the laterallyopposite sidewalls, wherein the metal gate contains columnar grains. 2.The apparatus of claim 1, wherein a dielectric layer is positionedbetween the semiconductor body and the metal gate.
 3. The apparatus ofclaim 2, wherein the dielectric layer comprises at least one of asilicon oxide, lanthanum oxide, tantalum oxide, titanium oxide, hafniumoxide, zirconium oxide, lead-zirconate-titanate,barium-strontium-titanate, or aluminum oxide.
 4. The apparatus of claim1, wherein a polysilicon layer is deposited on the metal gate.
 5. Asemiconductor apparatus comprising: a semiconductor body having a topsurface and laterally opposite sidewalls; a dielectric layer on the topsurface and the laterally opposite sidewalls of the semiconductor body;a metal gate layer with approximately equal thickness on a top surfaceand laterally opposite sidewalls of the dielectric layer, wherein themetal gate layer contains columnar grains; and a polysilicon layer onthe metal gate layer.
 6. The apparatus of claim 5, wherein thepolysilicon layer is doped.
 7. The apparatus of claim 5, wherein thethickness of the metal gate layer on the top surface and laterallyopposite sidewalls of the dielectric layer match within a maximumdeviation of +/−10%.